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mlc0xxb series 8-bit i/o type micro-cont roller with voice function this document contains information on a new product under development by megawin. megawin reserves the right to change or disco ntinue this product without notice. ? megawin technology co., ltd. 2007 all rights reserved. 2007/05 version 0.60 megawin features ? single chip 8-bit cpu ? operation voltage: 2.4v to 5.5v ? memory: ? rom (shared by program and data): 1024k ~ 48kbytes ? data ram: 256 bytes ? 24 input/output pins with wake-up function ? two power-down modes for saving power consumption: ? sleep mode: micro-controller no operation (main- and sub-oscillator still oscillating) ? stop mode: micro-controller no operation (all oscillators stop oscillating) ? two current dac output for voice synthesizer ? dual-channel melody with programmable envelope ? programmable sample rate for voice/melody function ? one serial input port and voltage comparator built-in ? three re-loadable 16-bit timers ? one watchdog timer built-in ? oscillator ? single or dual clock operation is selected by code option ? main oscillator operation at crystal or rc mode is selected by code option ? crystal/ceramic oscillator up to 4mhz @ 2.4v and 8mhz @ 3.6v ? rc oscillator up to 4mhz @ 2.4v selection information MLC331B mlc241b mls161b mlc121b rom (program rom) 1024k x 8-bit (32k x 8-bit) 768k x 8-bit (32k x 8-bit) 512k x 8-bit (32k x 8-bit) 384k x 8-bit (32k x 8-bit) i/o 24 24 24 24 6khz 4-bit adpcm 340 sec 250 sec 165 sec 125 sec voice duration 8khz 4-bit adpcm 250 sec 190 sec 125 sec 90 sec mlc081b mlc061b mlc041b mlc031b mlc021b mlc017b rom (program rom) 256k x 8-bit (32k x 8-bit) 192k x 8-bit (32k x 8-bit) 128k x 8-bit (32k x 8-bit) 96k x 8-bit (32k x 8-bit) 64k x 8-bit (32k x 8-bit) 48k x 8-bit (32k x 8-bit) i/o 24 24 24 24 24 24 6khz 4-bit adpcm 80 sec 60 sec 40 sec 30 sec 20 sec 16 sec voice duration 8khz 4-bit adpcm 60 sec 45 sec 30 sec 22 sec 16 sec 12 sec
2 mlc0xxb series technical summary megawin application field general voice synthesizer toy controller general ir controller general description mlc0xxb series integrates an 8-bit cpu core, sram, timer, d/a and system control circuits by a cmos silicon gate technology. the rom can store voice, melody, data table and program. twenty-four i/o pins can be used for keypad control, motor control, ir application, led indicators or communication with other systems. this chip can implement a dual tone melody function with programmable envelope, which can perform harmonic music with different timbres. this chip is very suitable for instruments, speech products, and intelligent educational toys, etc. pad description pad no. pad name i/o description 33, 4 agnd, gnd p ground pins, the two ground pins should be connected at the outside individually 35, 1 av dd , v dd p positive power pins, the two power pins should be connected at the outside individually 2, 3 osco, osci o, i rc or crystal oscillator pins 7, 8 x32o, x32i o, i 32.768khz crystal oscillator pins 5 /res i system reset pin (low active) 6 test - for test mode only 36 spk2 o dac 2 output 34 spk1 o dac 1 output 9 ~ 16 p0.0 ~ p0.7 i/o programmable i/o ports with interrupt function 25 ~ 32 p1.0 ~ p1.7 i/o programmable i/o ports. port p1.3, p1.4, p1.5 can be i/o or serial input port. port1.6, 1.7 can be output with ir carrier. 17 ~ 24 p2.0 ~ p2.7 i/o programmable i/o ports. port 2.4~2.6 can be i/o or voltage comparator.
megawin mlc0xxb series technical summary 3 block diagram tm0, 1, 2 rom cpu sram/register i/o, dac divider 0, 1 system clock generator tone gatting logic port 0.0 ~ 0.7 port 1.0 ~ 1.7 port 2.0 ~ 2.7 spk1 spk2 x32o x32i osco osci gnd vdd agnd avdd
4 mlc0xxb series technical summary megawin function description registers a y x p pch pcl 1 s accumulator the accumulator is a general-purpose 8-bit register, which stores the results of most arithmetic and logic operations. in addition, the accumulator usually contains one of two data words, which are used in these operations. index register (x, y) there are two 8-bit index registers (x and y), which may be used to count program steps or to provide an index value to be used in generating an effective address. when executing an instruction, which specifies indexed addressing, the cpu fetches the op code and the base address, and modifies the address by adding the index register to it prior to performing the desired operation. pre- or post-index of index address is possible. processor status register (p) the 8-bit processor status register contains seven status flags. some of the flags are controlled by the program, others may be controlled both the program and the cpu. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n v 1 b d i z c n: signed flag, 1 = negative, 0 = positive v: overflow flag, 1 = true, 0 = false b: brk interrupt command, 1 = brk, 0 = irqb d: decimal mode, 1 = true, 0 = false i: irqb disable flag, 1 = disable, 0 = enable z: zero flag, 1 = true, 0 = false c: carry flag, 1 = true, 0 = false
megawin mlc0xxb series technical summary 5 program counter (pc) the 16-bit program counter register provides the addresses, which step the micro-controller through sequential program instructions. each time the micro-controller fetches an instruction from program memory, the lower byte of the program counter (pcl) is placed on the low-order 8 bits of the address bus and the higher byte of the program counter (pch) is placed on the high-order 8 bits. the counter is incremented each time an instruction or data is fetched from program memory. stack pointer (s) the stack pointer is an 8-bit register, which is used to control the addressing of the variable-length stack. the stack pointer is automatically incremented and decremented under control of the micro-controller to perform stack manipulations under direction of either the program or interrupts (/nmi or /irq). the stack allows simple implementation of nested subroutines and multiple level interrupts. the stack pointer is initialized by the user?s software.
6 mlc0xxb series technical summary megawin memory map there are 256 bytes sram in mlc0xxb series. they are working ram (0000h to 007fh) and stacks (0180h to 01ffh). the address 0100h to 17fh are shared with address 0000h to 007fh. the address 00c0h to 00ffh and 0200h to 027fh are special function registers area. the bank select function, ranged from 4000h to 7fffh, is used for extending memories if the rom size is more than 32k bytes in mlc0xxb series. the default bank number is 00h after power on or reset. there are 1024k ~ 48k bytes program/data rom in mlc0xxb series. it is combined with 32k program/data rom and bank switching data rom. the rom address from 4000h to ffffh can store program, voice data, melody notes and other data. the address mapping of mlc0xxb series is shown as below. table bank 5 (041) zero page wr 0000h 007fh mlc0xxb series memory map 017fh 0100h 0080h~00bfh 00c0h~00ffh 0180h 01ffh stack area 0200h 027fh special function register sfr 4000h bfffh c000h interrupt vector area . . . table bank 0 (017) table bank 45 (241) 2 3 (031) program/table 0300h 7fffh ffeeh ~ ffefh fffeh ~ ffffh 3fffh 8000h table bank 1 (021) - program/table . . . table bank 61 (331) . . . share area ffedh
megawin mlc0xxb series technical summary 7 special function register (sfr) the address 00c0h to 00ffh and 0200h to 027fh are reserved for special function registers (sfr). the sfr is used to control or store the status of i/o, timers, system clock and other peripheral. sfr (special function register): 00c0h ~ 00ffh (page 0 area) address content default address content default 00c0 nmi_sel 00 00d0 bank 00 00c1 x 00d1 x 00c2 irq_en / irq_st 00 00d2 x 00c3 irq_clr 00 00d3 x 00c4 tm0l 00 00d4 x 00c5 tm0h 00 00d5 p1_mfr 00 00c6 tm0_ctl 00 00d6 p2_mfr 00 00c7 tm0_mod 00 00d7 x 00c8 tm1l 00 00d8 p0 00 00c9 tm1h 00 00d9 p1 00 00ca tm1_ctl 00 00da p2 00 00cb x 00db x 00cc div0_st / div0x_sel 00 00dc x 00cd x 00dd x 00ce div1_stl/ div1x_sel 00 00de wdt_ctl 00 00cf div1_sth 00 00df wdt_clr 00 address content default address content default 00e0 x 00f0 x 00e1 ch1 00 00f1 x 00e2 x 00f2 x 00e3 ch2 00 00f3 x 00e4 x 00f4 x 00e5 ch3 00 00f5 x 00e6 x 00f6 x 00e7 x 00f7 x 00e8 tm2_l 00 00f8 cmp_ctl 00 00e9 tm2_h 00 00f9 db_tc 00 00ea tm2_ctl 00 00fa vt_ctl 00 00eb x 00fb x 00ec x 00fc x 00ed x 00fd dac_drv 00 00ee x 00fe x 00ef x 00ff x
8 mlc0xxb series technical summary megawin sfr (special function register): 0200h ~ 027fh address content default address content default 0200 pwr_cr 00 0210 x 0201 fcpu_sr 00 0211 x 0202 rlh_en 00 0212 x 0203 x 0213 x 0204 x 0214 x 0205 x 0215 x 0206 x 0216 x 0207 x 0217 x 0208 x 0218 x 0209 x 0219 x 020a x 021a x 020b x 021b x 020c x 021c x 020d x 021d x 020e x 021e x 020f x 021f x address content default address content default 0220 x 0230 x 0221 x 0231 x 0222 x 0232 x 0223 x 0233 x 0224 x 0234 x 0225 x 0235 x 0226 x 0236 x 0227 x 0237 x 0228 x 0238 x 0229 x 0239 x 022a x 023a x 022b x 023b x 022c x 023c x 022d x 023d x 022e x 023e x 022f x 023f x
megawin mlc0xxb series technical summary 9 special function register, continued address content default address content default 0240 p0cr 00 0250 x 0241 p0mr 00 0251 x 0242 x 0252 x 0243 x 0253 x 0244 p1cr 00 0254 x 0245 p1mr 00 0255 x 0246 x 0256 x 0247 x 0257 x 0248 p2cr 00 0258 x 0249 p2mr 00 0259 x 024a x 025a x 024b x 025b x 024c x 025c x 024d x 025d x 024e x 025e x 024f x 025f x address content default address content default 0260 x 0270 x 0261 x 0271 x 0262 x 0272 x 0263 x 0273 x 0264 x 0274 x 0265 x 0275 x 0266 x 0276 x 0267 x 0277 x 0268 x 0278 x 0269 x 0279 x 026a x 027a x 026b x 027b x 026c x 027c x 026d x 027d x 026e x 027e x 026f x 027f x
10 mlc0xxb series technical summary megawin interrupt vectors vector address item priority properties memo fffch, fffdh reset 1 ext. initial reset fffah, fffbh nmi 2 int./ext. non-maskable interrupt vector fff8h, fff9h div0x 3 int. selectable divider 0 carry out interrupt fff6h, fff7h tm0 4 int. timer 0 overflow interrupt fff4h, fff5h p0 5 ext. port p0 interrupt vector fff2h, fff3h tm1 6 int. timer 1 overflow interrupt fff0h, fff1h tm2 7 int. timer 2 overflow interrupt ffeeh, ffefh div1x 8 int. selectable divider 1 carry out interrupt there are eight kinds of interrupt sources are provided in mlc0xxb series. the flag irq_en and irq_st are used to control the interrupts. when flag irq_st is set to ?1? by hardware and the corresponding bits of flag irq_en has been set by software, an interrupt is generated. when an interrupt occurs, all of the interrupts are inhibited until the cli or sta irq_en, #i instruction is invoked. executing the sei instruction can also disable the interrupts. interrupt process logic irq_en.0 interrupt vector generator logic initial reset sta irq_en, #i enable irq_st.0 nmi_ev initial reset sta irq_clr, #i sei instruction disable divider0 overflow signal timer0 underflow signal selectable nmi irq_en.1 s r q s r q s r q irq_st.1 irq_st.5 irq_en.5 s r q . . . cli instruction fffch, fffdh fffah, fffbh fff8h, fff9h fff6h, fff7h fff4h, fff5h fff2h, fff3h fff0h, fff1h ffeeh, ffefh nmi process logic divider1 overflow signal
megawin mlc0xxb series technical summary 11 interrupt registers nmi select flag address register 7 6 5 4 3 2 1 0 r w 00c0h nmi_sel - - - - - nis2 nis1 nis0 nis2 nis1 nis0 selected nmi source 0 0 0 none (default) 0 0 1 tm0 0 1 0 div0x 0 1 1 p0 1 0 0 tm1 1 0 1 tm2 1 1 0 div1x 1 1 1 (none) this register is used to select the nmi trigger source. the nmi is a rare resource of this system. only one trigger source is selected at one application is recommended. if over one trigger source is needed in some special application s , program must to distinguish the additional interrupter. after nmi occurs, program has to read nmi_sel register to know which source triggering nmi. irq enable flag address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c2h irq_en - - div1x tm2 tm1 p0 tm0 div0x - program can enable or disable the ability of triggering irq through this register. 0: disable (default ?0? at initialization) 1: enable p0: raising or falling edge occurs at port 0 input mode tm0, tm1, tm2: timer 0/1/2 underflow div0x, div1x: divider 0/1 selected interrupt frequency occurred irq status flag (same address with irq_en) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c2h irq_st - - div1x tm2 tm1 p0 tm0 div0x - when irq occurs, program can read this register to know which source triggering irq. irq clear flag address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c3h irq_clr - - div1x tm2 tm1 p0 tm0 div0x - program can clear the interrupt event by writing ?1? into the corresponding bit.
12 mlc0xxb series technical summary megawin div0 interrupt selector (clock source: f osc ) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00cch div0_st f osc /256 f osc /128 f osc /64 f osc /32 f osc /16 f osc /8 f osc /4 f osc /2 - 00cch div0x_sel - - - - - - cko1 cko0 - the divider 0 is organized as an 8-bit binary up counter, which is designed to generate periodic interrupts. when the main oscilla tor starts action, the divider 0 is incremented by each clock (f osc ). the contents of divider 0 can be reset to 00h by por, reset, waken from stop mode and change the contents of div0x_sel. cko1 cko0 selected div0x frequency 0 0 f osc / 32 0 1 f osc / 64 1 0 f osc / 128 1 1 f osc / 256 div0_st (8-bit) fosc div0 div0 rst fosc/1, /2, /4, /8 (for tm1) fosc/1, /2, /4, /8 (for tm0) fosc/1, /2, /4, /8 (for tm2) fosc/1, /2, /4, /8, /16, /32, /64, /128 (for div1) fosc/1, /2, /4, /8 fcpu to div1 to tm2 to tm1 to tm0 fosc/32, /64, /128, /256 (for div0x) div0x div0x_sel.0 div0x_sel.1 fcpu_sr.0 fcpu_sr.1 tm0_ctl.0 tm0_ctl.1 tm0_ctl.2 tm2_ctl.0 tm2_ctl.1 tm2_ctl.2 tm1_ctl.0 tm1_ctl.1 tm1_ctl.2 tm0_uv vss /p1.4 fx32 tm1_uv div1x_sel.6 div1x_sel.5 div1x_sel.4 fx32 fcpu_sr.2 vdd p1.4 div1_stl (8-bit) 16k, 8k, 4k, 2k, 1k, 512, 256, 128 fx32 div1_sth (8-bit) 64, 32, 16, 8, 4, 2, 1, 0.5 div1 fosc/1, /2, /4, /8, /16, 32, /64, /128 div1x sel 7 div1x div1 rst div1x_sel.0 div1x_sel.1 div1x_sel.2 div1x_sel.3
megawin mlc0xxb series technical summary 13 div1 interrupt selector (if the frequency of divider 1 clock source is 32.768khz) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00ceh div1_stl 128 hz 256 hz 512 hz 1024 hz 2048 hz 4096 hz 8192 hz 16384 hz - 00cfh div1_sth 0.5hz 1hz 2hz 4hz 8hz 16hz 32hz 64hz - 00ceh div1x_sel cki7 cki6 cki5 cki4 cko3 cko2 cko1 cko0 - the divider 1 contents can be reset to 00h by por, reset, waken from stop mode and writing div1x_sel register any value. cki7: select the input clock source of divider 1. 0: f osc/x (00ce h) , 1: f x32 cki6 cki5 cki4 selected div1 input frequency 0 0 0 f osc / 1 0 0 1 f osc / 2 0 1 0 f osc / 4 0 1 1 f osc / 8 1 0 0 f osc / 16 1 0 1 f osc / 32 1 1 0 f osc / 64 1 1 1 f osc / 128 cko3 cko2 cko1 cko0 selected div1x frequency 0 0 0 0 f div1 / 2 (16384 hz) 0 0 0 1 f div1 / 4 (8192 hz) 0 0 1 0 f div1 / 8 (4096 hz) 0 0 1 1 f div1 / 16 (2048 hz) 0 1 0 0 f div1 / 32 (1024 hz) 0 1 0 1 f div1 / 64 (512 hz) 0 1 1 0 f div1 / 128 (256 hz) 0 1 1 1 f div1 / 256 (128 hz) 1 0 0 0 f div1 / 512 (64 hz) 1 0 0 1 f div1 / 1024 (32 hz) 1 0 1 0 f div1 / 2048 (16 hz) 1 0 1 1 f div1 / 4096 (8 hz) 1 1 0 0 f div1 / 8192 (4 hz) 1 1 0 1 f div1 / 16384 (2 hz) 1 1 1 0 f div1 / 32768 (1 hz) 1 1 1 1 f div1 / 65536 (0.5 hz)
14 mlc0xxb series technical summary megawin watchdog timer (wdt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00deh wdt_ctl rsts - - - - rsel cki1 cki0 00dfh wdt_clr clr - - - bit 3 bit 2 bit 1 bit 0 rsts: wdt reset status, set by hardware when wdt overfl ows, clear by hardware reset or set wdt_clr.7 to one to clear this bit (this bit is read only) rsel: wdt reset selector, = 0 reset whole chip except rsts (wdt_ctl.7) = 1 reset pc and irq_en only cki1, cki0: wdt clock selector, = 00 f div1 /16384 selected (8 s @ f div1 = 32k) = 01 f div1 /4096 selected (2 s @ f div1 = 32k) = 10 f div1 /1024 selected (0.5 s @ f div1 = 32k) = 11 f div1 /128 selected (62.5 ms @ f div1 = 32k) clr: rsts clear control bit, program can clear rsts by program "1" into this bit (this bit is write only) the watchdog timer (wdt), which is organized as a 4-bit counter, is designed to prevent the program from unknown errors. the wdt is enabling by code option. if the wdt overflows, the wdt reset function will be performed. the watchdog timer co ntrol register (wdt_ctl) controls the wdt reset function. rsts (wdt_ctl.7) is set by hardware when the wdt overflows and is cleared by store one to the bit 7 of wdt_clr register or hardware reset. there are two types of wdt reset, which is selected by rsel (bit2 of wdt_ctl). wdt overflow will cause two types reset depending on the setting of rsel ? if rsel is equal to 0, the reset is the same as hardware reset except the setting of wdt_ctl and wdt_clr; if rsel is equal to 1, the reset only acts on program counter (pc) and irq_en. the wdt clock frequency is decided by bit1 and bit0 of wdt_ctl register. store one to the bit 7 of wdt_clr register will also reset the contents of the wdt. in normal operation, the application program must reset wdt before it overflows. the organization of the divider1 and watchdog timer is shown as below. overflow signal wdt enable disable (option code = 0) qw1 qw2 qw4 qw3 rrrr system reset except wdt_ctl.7 (option code = 1) q1 q2 q9 q10 q11 q12 q14 q13 fdiv1 ... divider1 s r q hardware reset wdt_clr <- 8xh wdt_ctl.7 pc & irq_en reset (other peripheral unchanged) wdt_ctl.2 wdt_ctl.0 wdt_ctl.1 q15 q16 fdiv1/128 fdiv1/1024 fdiv1/4096 fdiv1/16384 q7 q8
megawin mlc0xxb series technical summary 15 system control registers bank select address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d0h bank - bk6 bk5 bk4 bk3 bk2 bk1 bk0 program can switch the memory bank through this register. after power on reset, this register in initialized as 00h. the maximum bank numbers in mlc0xxb series are show as below: part no. MLC331B mlc241b mlc161b mlc121b max. bank 11 1101b 10 1101b 01 1101b 01 0101b part no. mlc081b mlc061b mlc041b mlc031b mlc021b mlc017b max. bank 00 1101b 00 1001b 00 0101b 00 0011b 00 0001b 00 0000b for more detailed information, please refer to memory map description. power saving control address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 0200h pwr_cr - - - - - ckc1 ckc0 halt - ckc1 ckc0 system clock control 0 0 f osc enable, f x32 enable (dual mode) 0 1 f osc enable, f x32 disable (single mode) 1 0 f osc disable, f x32 enable (slow mode) 1 1 f osc disable, f x32 disable (stop mode) note: pwr_cr . ckc0 is inhibited when single clock mode is selected . halt: f cpu off-line control bit. 1: f cpu off-line, 0: f cpu on-line program can switch the normal operation mode to the power-saving mode for saving power consumption through this register. there are three power saving mode s in this system. slow mode : (pwr_cr. ckc1 = 1, pwr_cr. ckc0 = 0) the main uc clock ( f osc ) stops oscillating. only very low power is needed for uc to keep running. stop mode : (pwr_cr. ckc1 = 1, pwr_cr. ckc0 = 1) all system clocks stop oscillating. the uc can be awakened from stop mode by 3-ways: port 0 interrupt, hardware reset, or power-on reset. halt mode : (pwr_cr. halt = 1) the f cpu clock in off-line status. the oscillator(s) still oscillating if the pwr_cr. ckc1 , pwr_cr. ckc0 keep low. the uc can be awakened from halt mode by 3-ways: all interrupt events (div0x, div1x, timer 0, timer 1, timer 2, port 0), hardware reset, or power-on reset.
16 mlc0xxb series technical summary megawin f cpu selector address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 0201h fcpu_sr - - - - - cks2 cks1 cks0 - cks2: f cpu clock source select. 0: f osc /x (0201 h), 1:f x32 cks1 cks0 selected f osc /x (0201h) frequency 0 0 f osc / 1 (default) 0 1 f osc / 2 1 0 f osc / 4 1 1 f osc / 8 release halt mode enable flag address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 0202h rlh_en - - div1x tm2 tm1 p0 tm0 div0x - set irq_clr register to clear the halt release event. release halt status flag is the irq_st register.
megawin mlc0xxb series technical summary 17 timers/counters timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c4h tm0l t7 t6 t5 t4 t3 t2 t1 t0 00c5h tm0h t15 t14 t13 t12 t11 t10 t9 t8 00c6h tm0_ctl stc rl/s tkes tms1 tms0 tki2 tki1 tki0 00c7h tm0_mod - - - tkps srs - tdi1 tdi0 stc: start/stop counting. 1: start and pre-load the value to counter, 0: stop timer clock (set this bit to 1 will be ignored when this bit already set to 1) rl/s: auto-reload disable/enable. 1: disa ble auto-reload, 0: enable auto-reload tkes: event or series input clock-in trigger edge selector; 0: rising edge, 1: falling edge tms1 tms0 select tm0 operation mode 0 0 16-bit counter (default) 0 1 reserved 1 0 16-bit shift register (the f tm0_uv /2 circuit will be bypassed) 1 1 16-bit rotate register (the f tm0_uv /2 circuit will be bypassed) tki2 tki1 tki0 selected tm0 input clock source 0 0 0 f osc / 1 0 0 1 f osc / 2 0 1 0 f osc / 4 0 1 1 f osc / 8 1 0 0 v dd 1 0 1 f x32 1 1 0 p1.4 1 1 1 v ss tkps: exchange the clock and data path of timer 0. 0:default path, 1: exchanged path srs: shift register selector. 0: shift left, 1: shift right tdi1 tdi0 selected tm0 shift-in data source 0 0 v dd 0 1 p1.5 1 0 div0x 1 1 div1x
18 mlc0xxb series technical summary megawin timer1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c8h tm1l t7 t6 t5 t4 t3 t2 t1 t0 00c9h tm1h t15 t14 t13 t12 t11 t10 t9 t8 00cah tm1_ctl stc rl/s tkes tms1 - tki2 tki1 tki0 stc: start/stop counting. 1: start and pre-load the value to counter, 0: stop timer clock rl/s: auto-reload disable/enable. 1: disa ble auto-reload, 0: enable auto-reload tkes: event or series input clock-in trigger edge selector; 0: rising edge, 1: falling edge tms1 select tm1 operation mode 0 16-bit counter 1 16-bit shift right register (the f tm1_uv /2 circuit will be bypassed) tki2 tki1 tki0 selected tm1input clock source 0 0 0 f osc / 1 0 0 1 f osc / 2 0 1 0 f osc / 4 0 1 1 f osc / 8 1 0 0 tm0 underflow 1 0 1 f x32 1 1 0 /p1.4 1 1 1 v ss timer 1 is a 16-bit down-count counter. the counter underflow frequency of timer 1 can be calculated with the equation: f tm1_uv = f tm1 / (tm1+1) for example: (if f tm1 = 4.096mhz) tm1 frequency 00 00h invalid 00 01h 2.048mhz 00 02h 1.365mhz ? ? 00 ffh 16khz ? ? ff ffh 62.5hz the timer 1 also can be used as tone generator. it generates specific frequency of tone with square wave, but the frequency of specific tone is half of the overflow frequency. the example frequency table is shown as below:
megawin mlc0xxb series technical summary 19 set tm1_ctl to be 80h (enable counting and auto reload, source clock = 4.00mhz) tm1h tm1l underflow frequency tone freque ncy relative scale of tone 3bh bah 261.609 130.804 c3 (130.813) 38h 5eh 277.200 138.600 c3# (138.591) 35h 36h 293.643 146.821 d3 (146.832) ? ? ? ? ? 1dh dch 523.286 261.643 c4 (261.626) ? ? ? ? ? 0eh eeh 1046.572 523.286 c5 (523.251) ? ? ? ? ? 07h 77h 2093.144 1046.572 c6 (1046.502) ? ? ? ? ? 03h f4h 3952.569 1976.284 b6 (1975.533) 03h bch 4184.100 2092.050 c7 (2093.005) p1.3 tm0h (r) tm0h re-load buffer (w) tm0 underflow reload reload f tm0_uv / 2 tm0_ctl.4 tm0_ctl.6 tm0_ctl.7 control logic tm0l (r) tm0l re-load buffer (w) mux mux vdd p1.5 div0x div1x tm0_ctl.0 tm0 mux tm0_ctl.3 tm0_mod.4 fosc/1 fosc/2 fosc/4 fosc/8 fx32 p1.4 vdd vss tm0_ctl.4 tm0_ctl.2 tm0_ctl.1 tm0_mod.0 tm0_mod.1 ch1 tone p1.6 tm1l (r) tm1h (r) tm1l re-load buffer (w) tm1h re-load buffer (w) tm1 underflow reload reload tm1 f tm1_uv / 2 vdd mux tm1_ctl.4 tm1_ctl.4 tm1_ctl.6 tm1_ctl.7 control logic tm1_ctl.1 fx32 fosc/4 tm1_ctl.2 mux tm0 underflow fosc/1 fosc/2 fosc/8 tm1_ctl.0 /p1.4 vss tm2_ctl.1 ch2 tone p1.7 tm2l re-load buffer (w) tm2h re-load buffer (w) tm2l (r) tm2h (r) fx32 tm2 underflow reload reload fosc/4 tm2_ctl.2 tm2 mux tm0 underflow f tm2_uv / 2 fosc/1 fosc/2 fosc/8 tm2_ctl.0 tm1 underflow vss tm2_ctl.6 tm2_ctl.7 control logic
20 mlc0xxb series technical summary megawin timer2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00e8h tm2_l t7 t6 t5 t4 t3 t2 t1 t0 00e9h tm2_h t15 t14 t13 t12 t11 t10 t9 t8 00eah tm2_ctl stc rl/s - - - tki2 tki1 tki0 stc: start/stop counting. 1: start and pre-load the value to counter, 0: stop timer clock rl/s: auto-reload disable/enable. 1: disa ble auto-reload, 0: enable auto-reload tki2 tki1 tki0 selected tm2 input clock source 0 0 0 f osc / 1 0 0 1 f osc / 2 0 1 0 f osc / 4 0 1 1 f osc / 8 1 0 0 tm0 underflow 1 0 1 f x32 1 1 0 tm1 underflow 1 1 1 v ss i/o pin p0.n data bus buffer output p0mr.1 p0cr.x lda buffer, p0 instruction sta p0,#data instruction enable enable vdd input/output pin of the p0 p0mr.0 enable
megawin mlc0xxb series technical summary 21 i/o ports port 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d8h p0 p07 p06 p05 p04 p03 p02 p01 p00 0240h p0cr cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 0241h p0mr - mp06 mp05 mp04 - mp02 mp01 mp00 port 0 is an 8-bit i/o port; each pin can be programmed as input or output individually. p0cr: p0.0~p0.7 is input or output. 0: input, 1: output p0mr: p0.0~p0.7, pull-high, cmos /nmos and pull-high value setting p0mr.0: p0.0 ~ p0.3 pull-high control, 0: disable, 1:enable p0mr.1: p0.0 ~ p0.3 cmos/nmos selector, 0: cmos, 1:nmos p0mr.2: p0.0 ~ p0.3 pull-high resistor value control, 0: large, 1: small p0mr.4: p0.4 ~ p0.7 pull-high control, 0: disable, 1: enable p0mr.5: p0.4 ~ p0.7 cmos/nmos selector, 0: cmos, 1:nmos p0mr.6: p0.4 ~ p0.7 pull-high resistor value cont rol, 0: large, 1: small (350k or 50k selector) at initial reset, the port p0 is all in input mode. each pin of port p0 can be specified as input or output mode independently by the p0cr registers. when p0 is used as output port, cmos or nmos open drain output type can be selected by the p0mr register. port p0 has the internal pull-high resistors that can be enabled/disabled by specifying the p0mr.0 and p0mr.4 respectively. the pull-high resistors will be temporarily disable if the port is specified as output mode. the read value will be the contents of output buffer in output mode. when p0 port is used as input mode and the rlh_en, and irq_en corresponding to the p0 port are set, a signal change at the port p0 (any pin) will execute the halt mode release or interrupt subroutine. both the raising or falling signal will set the port p0 event. the schmitt trigger circuit is added in the input port part of all i/o pins. please set port 0 as output high before set it as input mode, if speeds up the internal pull-high effect is needed. if the i/o ports are not used in your applicati on, please set them as input with pull-high or output mode to avoid unnecessary power consumption.
22 mlc0xxb series technical summary megawin port 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d9h p1 p17 p16 p15 p14 p13 p12 p11 p10 0244h p1cr cp17 cp16 cp15 cp14 cp13 cp12 cp11 cp10 0245h p1mr - - mp15 mp14 - - mp11 mp10 port 1 is an 8-bit i/o port; refer to port 0 for more information. p1cr: p1.0 ~ p1.7 is input or output. 0: input, 1: output p1mr: p1.0 ~ p1.7, pull-high and cmos/nmos port 1 multi-function selector address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d5h p1_mfr ps7 ps6 - - ps3 - - - the port 1 can be programmed to special function via p1_mfr register. the serial input port is multiplex with p1.4 and p1.5 (p1.4/clk and p1.5/din), the event counte r input port is multiplex with p1.4 and p1.5, and the infrared control is multiplex with p1.3, p1.6 or p1.7 ps7, ps6, ps3: normal i/o or tm2/tm1/tm0 carrier output selector. 0:normal i/o, 1: carrier output port 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00dah p2 p27 p26 p25 p24 p23 p22 p21 p20 0248h p2cr cp27 cp26 cp25 cp24 cp23 cp22 cp21 cp20 0249h p2mr - - mp25 mp24 - - mp21 mp20 port 2 is an 8-bit i/o port; refer to port 0 for more information. p2cr: p2.0 ~ p2.7 is input or output. 0: input, 1: output p2mr: p2.0 ~ p2.7, pull-high and cmos/nmos port 2 multi-function selector (p2.4/v-, p2.5/v+, p2.6/vo) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d6h p2_mfr - ps6 - - - - - - ps6: normal i/o or voltage comparator output selector of port 2.6. 0:normal i/o, 1: comparator output
megawin mlc0xxb series technical summary 23 voltage comparator (p2.4/ v-, p2.5/ v+, p2.6/vo) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00f8h cmp_ctl - - - - - pwr - rlt pwr: voltage comparator power cont rol. 0: power-off, 1: power-on rlt: the voltage compare result. 0: v+ < v-, 1: v+ > v- p1.3 tm0l (r) tm0h (r) tm0l re-load buffer (w) tm0h re-load buffer (w) mux mux vdd p1.5 div0x div1x tm0 underflow tm0_ctl.0 tm0_ctl.1 tm0_mod.0 tm0_mod.1 reload reload tm0 f tm0_uv / 2 tm0_ctl.2 mux tm0_ctl.3 tm0_mod.4 tm0_ctl.4 tm0_ctl.4 use tm0 as serie s input buffer tm1_ctl.6 tm1_ctl.7 control logic fosc/1 fosc/2 fosc/4 fosc/8 f x32 p1.4 vdd vss i/o pin p2.4 data bus buffer output p2mr.1 p2cr.x lda buffer, p2 instruction sta p2,#data instruction enable vdd input/output pin of the p2 p2mr.0 enable + _ analog switch i/o pin p2.6 analog switch i/o pin p2.5 analog switch to p2.5 i/o store the compare result to a register bit vdd power control bit sel sel
24 mlc0xxb series technical summary megawin ch1 buffer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00e1h ch1 da7 da6 da5 da4 da3 da2 da1 da0 temporary speech data output buffer. for playing a voice, the program could be coded as below: lda pcm ; load pcm data into dac buffer sta e1h ; latch 8 -bit data (ch1) into dac1 if directly mode is selected. ch2, ch3 buffer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00e3h ch2/env2 da7 da6 da5 da4 da3 da2 da1 da0 00e5h ch3/env3 da7 da6 da5 da4 da3 da2 da1 da0 temporary speech data output buffer. ch3 tone vss ch2 tone vss tm1h (r) tm1h re-load buffer (w) tm2 underflow reload tm2 tm1 voice (l ch) data bus voice (r ch) ch1 buffer dac1 data latch control logic: 1. tm0 int. load 2. tm1 int. load 3. tm2 int. load 4. directly data latch control logic: 1. tm0 int. load 2. tm1 int. load 3. tm2 int. load 4. directly load shift load shift spk1 spk2 p1.6 tm1 underflow f tm1_uv / 2 tm1_ctl.4 tm1_ctl.6 tm1_ctl.7 control logic dac2 ch3 buffer ch2 buffer envelope process p1.7 tm2h re-load buffer (w) tm2h (r) reload f tm2_uv / 2 tm2_ctl.6 tm2_ctl.7 control logic vt_ctl.1 vt_ctl.2 mixer envelope process
megawin mlc0xxb series technical summary 25 the ch2 and ch3 buffers could work as envelope setting registers that designed to control the output level of tone. when they are set to be 80h, the output is at the lowest ? no any tone output. after stopping playing tone, the vt_ctl register should be set to voice mode and progress the fade out subroutine to avoid the noise burst. changing the envelope of a tone can create various timbre of music. the waveform of normal square wave is like: program can create such waveforms as below through the envelope setting register. (envelope a) (envelope b) the same tone with envelope a and b sounds very different. the tones with envelope-a sounds like piano and envelope-b sounds like harmonica.
26 mlc0xxb series technical summary megawin dac buffer transfer control address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00f9h db_tc - tc6 tc5 tc4 - tc2 tc1 tc0 tc6 ~ tc4 control ch2/ch3, tc2 ~ tc0 control ch1. before disable all the dac output, user must progress the fade out subroutine to avoid the noise burst. tc6: dac2 enable control. 0: disable, 1:enable tc5 tc4 dac 2 buffer transfer control 0 0 ch 2 / ch3 buffer data transfer to dac 2 after tm0 underflow 0 1 ch 2 / ch3 buffer data transfer to dac 2 after tm1 underflow 1 0 ch 2 / ch3 buffer data transfer to dac 2 after tm2 underflow 1 1 ch 2 / ch3 buffer data transfer to dac 2 directly tc2: dac1 enable control. 0: disable, 1:enable tc1 tc0 dac 1 buffer transfer control 0 0 ch 1 buffer data transfer to dac 1 after tm0 underflow 0 1 ch 1 buffer data transfer to dac 1 after tm1 underflow 1 0 ch 1 buffer data transfer to dac 1 after tm2 underflow 1 1 ch 1 buffer data transfer to dac 1 directly voice/tone control address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00fah vt_ctl - - - - - vts3 vts2 - ch3, ch2 voice/tone path control register . vts3: ch 3 voice/tone control. 0: voice, 1:tone vts2: ch 2 voice/tone control. 0: voice, 1:tone dac output current address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00fdh dac_drv - - - - - - drv1 drv0 program can select the driving current of dac output to fit different bipolar junction transistor for generating appropriate sound quality. drv1 drv0 dac output drive current (v dd = 3.0v) 0 0 1.30 ma (default) 0 1 1.84 ma 1 0 2.60 ma 1 1 3.67 ma
megawin mlc0xxb series technical summary 27 programming notice the status after different reset condition is listed below: power on reset cpu /rst pin reset sram data unknown unchanged cpu register unknown unknown special function register default value default value mask option clock source single / dual fosc rc / crystal wdt enable / disable application circuit 1 2 34 a b c d 4 3 2 1 d c b a title number revision size a4 date: 16-may-2007 sheet of file: e:\user\feng\sch\mlc081 series\c081bsap.ddb drawn by: vcc c6 0.1uf c1 47uf r7 620 r6 620 q1 8050s q2 8050s vcc vcc r1 430k spk1 spk2 spk1 spk2 p0.0 p0.1 p0.2 p0.3 p1.2 vcc p0.0 p0.1 p0.2 p0.3 s11 s15 s07 s03 s02 s01 s00 s06 s05 s04 s10 s09 s08 s14 s13 s12 led 4 led 3 led 2 led 1 p0.0 p0.1 p0.2 p0.3 p0.0 p0.1 p0.2 p0.3 p0.0 p0.1 p0.2 p0.3 vcc a - + m1 c8 0.1u q3 8550 c7 0.1u vcc spk1 8 ohm spk2 8 ohm spk2 36 avdd 35 spk1 34 agnd 33 p1.7 32 p1.6 31 p1.5 30 p1.4 29 p1.3 28 p1.2 27 p1.1 26 p1.0 25 p2.7 24 p2.6 23 x32i 8 p0.0 9 p0.1 10 p0.2 11 p0.3 12 p0.4 13 p0.5 14 vdd 1 osco 2 osci 3 gnd 4 res 5 test 6 x32o 7 p2.5 22 p2.4 21 p2.3 20 p2.2 19 p2.1 18 p2.0 17 p0.7 16 p0.6 15 u1 mlc0xxb_cob @4mhz r8 470 x1 32.768khz c4 20pf c5 20pf r11 560 r10 560 r9 470 r5 200 r4 200 r3 200 r2 200 q4 8550 q5 8050s q6 8050s p1.2 mlc0xxb series typical application circuit a r12 750k aa x 3 4.5v a - + m2 q8 8050s r14 100 r15 1 vcc c10 47uf
28 mlc0xxb series technical summary megawin pad assignment p0.3 p0.2 p0.1 p0.0 x32i x32o test /res gnd osci(r) osco vdd p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 agnd spk1 avdd spk2 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 p0.7 p0.6 p0.5 p0.4 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 10 9 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 (0,0)
megawin mlc0xxb series technical summary 29 absolute maximum rating parameter rating unit supply voltage to ground potential -0.3 to +5.0 v applied input / output voltage -0.3 to +5.0 v power dissipation 60 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. dc characteristics (v dd -v ss = 3.0 v, f osc = 4mhz, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage v dd - 2.4 - 5.5 v op. current i op no load (ext.-v) in normal operation - 1.5 5.1 ma standby current i stb no load (ext.-v) - 1 3 a dac_drv = 00h - 1.30 - dac_drv = 01h - 1.84 - dac_drv = 02h - 2.60 - dac output driving current i dac dac_drv = 03h - 3.67 - ma input high voltage v ih - 0.8 v dd - v dd v input low voltage v il - 0 - 0.2v dd v port 0, 1, 2 drive current i oh v oh = 2.7v, v dd = 3.0v - 1.5 - ma port 0, p1.4~1.7, p2.4~2.7 sink current i ol0 v ol = 0.4v, v dd = 3.0v - 3.0 - ma port 1.0~1.3, 2.0~2.3 sink current i ol1 v ol = 0.4v, v dd = 3.0v - 9.0 - ma internal pull-high resistor (l) r ph0 v il = 0v - 350k - ? internal pull-high resistor (s) r ph1 v il = 0v, port 0 only - 50k - ? ac characteristics parameter sym. conditions min. typ. max. unit rc/crystal, v dd = 3.0v 0.5 4 - cpu op. frequency f cpu rc/crystal, v dd = 5.0v 0.5 8 - mhz frequency deviation by voltage drop for rc oscillator ? f f f(3.0v) - f(2.4v) f(3.0v) - 2 4 % por duration t por f osc = 4 mhz 10 15 50 ms
30 mlc0xxb series technical summary megawin history: v0.10: original v0.20: add ffedh on the memory map diagram (page 6) v0.30: correct the srs function definition (page 17, set this bit to 1 should be shift right) v0.40: add the description about the output mode of i/o port (page 21) v0.50: modify the typing error of page 21 (change 100k to 350k) v0.60: modify some typing mistakes

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